The serial digital interface (SDI) at 3 Gb/sec was introduced to allow production and transmission of high-definition content at higher frame rates (e.g., 1080 p at 50 fps and 60 fps), higher bit depths (e.g., 12 bits per component), and to provide support for R′G′B′ and 4:4:4:4 processing. The bandwidth requirements to transmit these video formats in serial digital form exceed the capabilities of a single SMPTE 292M interface. One solution to that problem is the use of two SMPTE 292M 1.5-Gb/sec links (i.e., dual-link), as specified in SMPTE 372M. However, dual-link interfaces are expensive to implement, as two sets of semiconductor devices are required to support each 1.5-Gb/sec link. Additional complexity is introduced by formatting 1080 p data per SMPTE 372M, as the data must be line demultiplexed for transmission, and re-multiplexed prior to image processing and display.
The data mapping standard for 3 Gb/sec SDI is defined in SMPTE 425M. Within this standard, Level A represents the direct image format (component) mapping, where the video signal components (R, G, B or Y, Cb, Cr) are directly mapped onto two 10-bit parallel data streams. Level B in the standard represents 2×SMPTE 292M HD SDI mapping, which allows for transmission of two parallel 10-bit interfaces of the same line and frame structure, constructed in conformance with SMPTE 292M. Level B also includes support for dual-link video.
Level A mapping has the advantage of allowing the transmitter and receiver to handle video data in component form and interface directly with other Level A compliant equipment, such as image processors. Level B mapping has the advantage of allowing easy conversion between the 3 Gb/sec SDI link and dual-link equipment. However, a fundamental incompatibility between the two mapping options exists, because Level A formatted data retains each video component separately whereas Level B formatted data does not. If the customer's video system requires conversion between the two mapping formats, this is a non-trivial exercise that requires considerable hardware resources.
If a serializer does not have the capability to perform the Level A format to Level B format mapping conversion internally, a secondary device (such as an FPGA) is required in the customer's system to allow interfacing with a Level B serial link. Eliminating the requirement for this FPGA reduces customers' system costs, and simplifies the overall system. Similarly, if the receiver does not have the capability to perform the Level B format to the Level A format mapping conversion internally, a secondary device (such as an FPGA) will be required in the customer's system to allow interfacing with an image processor. Eliminating the requirement for this FPGA also reduces customers' system costs, and simplifies the overall system.
Although solutions exist in the marketplace that allow for single-link to dual-link conversion of 3 Gb/sec SDI video and vice-versa, the existing solutions do not support the capability to convert between Level B and Level A mappings.